Field of the Invention (Technical Field)
The present invention relates to vias for three dimensional (3D) stacking, packaging and/or heterogeneous integration of semiconductor devices and/or wafers. In particular, the invention relates to a process for the manufacture of a via, to a via, to a 3D circuit and to a semiconductor device, including but not limited to a MEMS (Micro-Electro-Mechanical System).
Description of Related Art
Vias are interconnects used to vertically interconnect chips, devices, interconnection layers and wafers, i.e., in an out-of-plane direction. This may be done either electrical, optical or through micro-fluidic channels.
State of the art vias include through-silicon vias (TSVs). TSVs are vias that pass through a silicon wafer in order to establish an electrical connection from the active side to the backside of a die. A disadvantage of TSVs is that significant difficulties are often involved with TSV fabrication such as the conformal coverage of complex surfaces, filling of narrow high-aspect-ratio structures, wafer thinning and cracking of the wafer due to material property mismatch with an interposer (e.g., copper) used to form the electrical connection. Furthermore, accurate placement and the electrical connection of the TSV interposer with an interconnect layer is a challenge in itself.
Another approach is the through mold via (TMV). TMVs are typically formed using a process for epoxy-molding-compound drilling and residue cleaning. Once channels are formed, the vias are completed by filling with solder using for example a screen printing process. This process is not very suitable for 3D integration due to the large diameter of the channel of the via (d≧450 μm), low aspect ratio (1:1) and the high resistance of the solder.
WO 2006/039633 A2 recites a structure and method of making an interconnect element and multilayer wiring board including the interconnect element. US 2006/0267213 A1 recites a stackable tier structure comprising prefabricated high density feedthrough. US 2008/0170819 A1 recites an optical element, packaging substrate and device for optical communication. The packaging substrate has a via with a resin filling and a conductor. US 2003/0139032 A1 recites a metal post manufacturing method. US 2003/0173676 A1 recites a multi-layered semiconductor device and method of manufacturing same. US 2010/0218986 A1 recites a method for manufacturing printed wiring board and printed wiring board.